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Welcome to CS2100DE! In this website and accompanying repository, you will find all the materials for the labs for CS2100DE.
Intended learning outcomes (labs)
In the lab component of this course, you will put into practice the concepts learned in the lecture, and see them come to life.
You will learn:
- What an FPGA is, and how to use them and their accompanying tools and software
- How to design simple (and not-so-simple) logic circuits with SystemVerilog
- The RISC-V architecture and assembly language
- How to build your very own CPU which can execute real RISC-V programs!
First steps
To make the most of the labs, we recommend doing some reading before you come for your first session.
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First, the page on how to use this website. Pay special attention to the section on "How to get help", as it is very important.
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Next, the prerequisites for the lab. If you have any concerns with these prerequisites, please approach the teaching team as early as possible.
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You should also read the grading scheme for lab assignments and projects.
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Finally, make sure you read Getting to know your Nexys 4 and install Vivado on your personal computer as soon as possible. If you do not have access to a Windows or Linux (preferred) PC, you should try your best to get/borrow one for this course.
Lab Schedule and Outline
| Week | Lab Date | Activity | Remarks |
|---|---|---|---|
| 1 | 17 Jan 2025 | Nil | |
| 2 | 24 Jan 2025 | Nil | |
| 3 | 31 Jan 2025 | Getting familiar with FPGA tools | |
| 4 | 07 Feb 2025 | Playing with the 7-segment display | |
| 5 | 14 Feb 2025 | Creating more complex logic | |
| 6 | 21 Feb 2025 | Introduction to RISC-V Assembly | |
| 7 | 07 Mar 2025 | Decoding RISC-V Instructions | |
| 8 | 14 Mar 2025 | Designing our ALU | |
| 9 | 21 Mar 2025 | The data path | |
| 10 | 28 Mar 2025 | NUS Well-being day - go rest! | |
| 11 | 04 Apr 2025 | The Finale | |
| 12 | 11 Apr 2025 | Project demonstration | |
| 13 | 18 Apr 2025 | Good Friday - be free :3 |